The present invention relates to a driving system for an electrical power conversion equipment, and in particular, it is preferably applied to a driving system of a switching device at the start of or during a resonant operation in a resonance or pseudo resonance source in an electric power conversion equipment.
There are a switching power supply and an inverter etc., which use a resonance operation or a pseudo resonance operation for an electrical power conversion equipment. In a certain driving system for a switching power supply for example, switching control is carried out while performing a resonant operation or a pseudo resonant operation to reduce the loss of a switching device. Namely, in the resonant operation, the state in which the current or the voltage of the switching device becomes zero is intermittently brought about. When the current or the voltage of the switching device becomes zero, the switching device is made turned-on or turned-off, by which the loss of the switching device can be made zero. In the pseudo resonant operation, when the current or the voltage of the switching device becomes zero, the switching device is made turned-on, by which the loss at the turning-on of the switching device can be made zero (Patent Document 1: Japanese Unexamined patent Application Publication No. JP-A-2002-209381 (corresponding to U.S. Pat. No. 6,483,722)).
FIG. 10 is a block diagram schematically showing the configuration of a switching power supply for performing a resonant operation.
In FIG. 10, the switching power supply is provided with switching devices Q1, Q2, which are connected in series with each other. Along with this, to the switching device Q1, an LC series resonance circuit formed of a capacitor C and a reactor L is connected in parallel. For each of the switching devices Q1, Q2, there can be used an insulated gate power device such as an IGBT (Insulated Gate Bipolar Transistor) or a power MOSFET, for example.
The gates of the switching devices Q1, Q2 are connected to a driving control section 3 through driver circuits 5, 4, respectively. Here, to the driving control section 3, an input detecting section 1 is connected which detects whether the drain current Id or the drain voltage Vds of the switching device Q1 is zero or not. Along with this, a trigger outputting section 2 is also connected which outputs a trigger signal S3 making the resonant operation of the LC series resonance circuit start.
Moreover, the trigger signal S3 outputted from the trigger outputting section 2 makes the switching device Q1 turned-on, which starts up the switching power supply. At this time, the switching device Q2 remains turned-off. This makes a current flow in the LC series resonance circuit through the switching device Q1, by which the LC series resonance circuit starts a resonant operation.
Upon the resonant operation of the LC series resonance circuit, the input detecting section 1 detects the drain current Id and the drain voltage Vds, and outputs the detected results to the driving control section 3. Then, the driving control section 3 detects a timing at which the drain current Id or the drain voltage Vds becomes zero to make the switching device Q1 turned-on and turned-off, by which the driving control section 3 can carry out switching control of the switching device Q1 while making the loss of the switching device Q1.
FIG. 11 is a block diagram schematically showing an example of the configuration of a related driving system for a switching power supply.
In FIG. 11, a driver circuit 111 is provided with a preliminary driver 112 and a main driver 113. The driver circuit 111 can be used as the driver circuit 5 shown in FIG. 10.
The preliminary driver 112 is provided with a logic inverting circuit L41. Along with this, the main driver 113 is provided with a buffer L42, a p-channel transistor MP41 and an n-channel transistor MN41. The p-channel transistor MP41 is formed of a plurality of p-channel unit transistors connected in parallel and the number mp thereof can be taken as, for example, 1000. The p-channel transistor MP41 and the n-channel transistor MN41 are connected in series. To the gates of the p-channel transistor MP41 and the n-channel transistor MN41, the output terminal of the logic inverting circuit L41 is connected through the buffer L42. Moreover, the input terminal of the logic inverting circuit L41 is connected to a driving signal input terminal T1 and the connection point of the p-channel transistor MP41 and the n-channel transistor MN41 is further connected to a switching device driving terminal T2.
FIG. 12 is a diagram showing waveforms of signals in various sections of the driving system of the switching power supply shown in FIG. 11.
In FIG. 12, at the start of the resonant operation R1, the trigger signal S3 is outputted from the trigger outputting section 2 shown in FIG. 10 to change the level of the trigger signal S3 from a low level to a high level (t1). The trigger signal S3 outputted from the trigger outputting section 2 makes a driving signal S1 outputted from the driving control section 3 to the driver circuit 111 to change the level of the electric potential at the driving signal input terminal T1 from a low level to a high level. Then, the change in the level of the electric potential at the driving signal input terminal T1 from the low level to the high level makes the change in the level of the electric potential transmitted to the gates of the p-channel transistor MP41 and the n-channel transistor MN41 through the logic inverting circuit L41 and the buffer L42 to turn-on the p-channel transistor MP41 and, along with this, to turn-off the n-channel transistor MN41. This makes the level of the electric potential at the switching device driving terminal T2 gradually shift from a low level to a high level according to the driving capacity of the p-channel transistor MP41 (t1 to t3).
The gradual shift of the level of the electric potential at the switching device driving terminal T2 from the low level to the high level gradually shifts the level of the drain voltage Vds of the switching device Q1 shown in FIG. 10 from a high level to a low level (t2 to t3) and, along with this, gradually increases the drain current Id of the switching device Q1 (t2 to t5).
Next to this, the change in the level of the trigger signal S3 from the high level to the low level (t4) changes the level of the electric potential at the driving signal input terminal T1 from the high level to the low level. Then, the change in the level of the electric potential at the driving signal input terminal T1 from the high level to the low level makes the change in the electric potential transmitted to the gates of the p-channel transistor MP41 and the n-channel transistor MN41 through the logic inverting circuit L41 and the buffer L42 to turn-off the p-channel transistor MP41 and, along with this, to turn-on the n-channel transistor MN41. This makes the level of the electric potential at the switching device driving terminal T2 shift from the high level to the low level (t4 to t5).
The shift of the level of the electric potential at the switching device driving terminal T2 from the high level to the low level shifts the level of the drain voltage Vds of the switching device Q1 shown in FIG. 10 from the low level to the high level (t5 to t6) and, along with this, decreases the drain current Id of the switching device Q1 (t5 to t6).
Following this, during a resonant operation R2, by the resonant operation of the LC series resonance circuit, the level of the drain voltage Vds of the switching device Q1 shifts from the high level to the low level (t7 to t8). The drain voltage Vds of the switching device Q1 is detected by the input detecting section 1 and the detected signal is outputted to the driving control section 3. Then, at a timing at which the level of the drain current Id or the drain voltage Vds of the switching device Q1 becomes zero, the driving signal S1 is outputted from the driving control section 3 to the driver circuit 111 to change the level of the electric potential at the driving signal input terminal T1 from the low level to the high level (t8).
The change in the level of the electric potential at the driving signal input terminal T1 from the low level to the high level makes the change in the level of the electric potential transmitted to the gates of the p-channel transistor MP41 and the n-channel transistor MN41 through the logic inverting circuit L41 and the buffer L42 to turn-on the p-channel transistor MP41 and, along with this, to turn-off the n-channel transistor MN41. This makes the level of the electric potential at the switching device driving terminal T2 gradually shift from the low level to the high level according to the driving capacity of the p-channel transistor MP41 (t8 to t9).
The gradual shift of the level of the electric potential at the switching device driving terminal T2 from the low level to the high level gradually increases the drain current Id of the switching device Q1 (t8 to t11). Here, when the p-channel transistor MP41 has a low driving capacity to prolong the duration until the level of the electric potential at the switching device driving terminal T2 shifts from the low level to the high level, a switching is carried out when the drain voltage Vds of the switching device Q1 is not zero to increase a switching loss N1.
Subsequent to this, the change in the level of the electric potential at the driving signal input terminal T1 from the high level to the low level (t10) makes the change in the level of the electric potential transmitted to the gates of the p-channel transistor MP41 and the n-channel transistor MN41 through the logic inverting circuit L41 and the buffer L42 to turn-off the p-channel transistor MP41 and, along with this, to turn-on the n-channel transistor MN41. This makes the level of the electric potential at the switching device driving terminal T2 shift from the high level to the low level (t10 to t11).
Then, the shift of the level of the electric potential at the switching device driving terminal T2 from the high level to the low level shifts the level of the drain voltage Vds of the switching device Q1 shown in FIG. 10 from the low level to the high level (t11) and, along with this, decreases the drain current Id of the switching device Q1 (t11).
FIG. 13 is a block diagram schematically showing another example of the configuration of a related driving system for a switching power supply.
In FIG. 13, a driver circuit 121 is provided with a preliminary driver 122 and a main driver 123. The driver circuit 121 can be used as the driver circuit 5 shown in FIG. 10.
The preliminary driver 122 is provided with a logic inverting circuit L43. Along with this, the main driver 123 is provided with a buffer L44, a p-channel transistor MP42 and an n-channel transistor MN42. The p-channel transistor MP42 is formed of a plurality of p-channel unit transistors connected in parallel and the number mp thereof can be taken as, for example, 4000. The p-channel transistor MP42 and the n-channel transistor MN42 are connected in series. To the gates of the p-channel transistor MP42 and the n-channel transistor MN42, the output terminal of the logic inverting circuit L43 is connected through the buffer L44. Moreover, the input terminal of the logic inverting circuit L43 is connected to a driving signal input terminal T1 and the connection point of the p-channel transistor MP42 and the n-channel transistor MN42 is further connected to a switching device driving terminal T2.
FIG. 14 is a diagram showing waveforms of signals in various sections of the driving system of the switching power supply shown in FIG. 13.
In FIG. 14, at the start of the resonant operation R1, the trigger signal S3 is outputted from the trigger outputting section 2 shown in FIG. 10 to change the level of the trigger signal S3 from a low level to a high level (t1). The trigger signal S3 outputted from the trigger outputting section 2 makes the driving signal S1 outputted from the driving control section 3 to the driver circuit 121 to change the level of the electric potential at the driving signal input terminal T1 from a low level to a high level. Then, the change in the level of the electric potential at the driving signal input terminal T1 from the low level to the high level makes the change in the level of the electric potential transmitted to the gates of the p-channel transistor MP42 and the n-channel transistor MN42 through the logic inverting circuit L43 and the buffer L44 to turn-on the p-channel transistor MP42 and, along with this, to turn-off the n-channel transistor MN42. This makes the level of the electric potential at the switching device driving terminal T2 gradually shift from a low level to a high level according to the driving capacity of the p-channel transistor MP42 (t1 to t3).
The gradual shift of the level of the electric potential at the switching device driving terminal T2 from the low level to the high level gradually shifts the drain voltage Vds of the switching device Q1 shown in FIG. 10 from a high level to a low level (t2 to t3) and, along with this, gradually increases the drain current Id of the switching device Q1 (t2 to t5). Here, when the p-channel transistor MP42 has a high driving capacity to shorten the duration until the level of the electric potential at the switching device driving terminal T2 shifts from the low level to the high level, a peak in the drain current Id of the switching device Q1 becomes large thereby increasing a switching noise N2.
Next, the change in the level of the trigger signal S3 from the high level to the low level (t4) changes the level of the electric potential at the driving signal input terminal T1 from the high level to the low level. Then, the change in the level of the electric potential at the driving signal input terminal T1 from the high level to the low level makes the change in the electric potential transmitted to the gates of the p-channel transistor MP42 and the n-channel transistor MN42 through the logic inverting circuit L43 and the buffer L44 to turn-off the p-channel transistor MP42 and, along with this, to turn-on the n-channel transistor MN42. This makes the level of the electric potential at the switching device driving terminal T2 shift from the high level to the low level (t4 to t5).
The shift of the level of the electric potential at the switching device driving terminal T2 from the high level to the low level shifts the level of the drain voltage Vds of the switching device Q1 shown in FIG. 10 from the low level to the high level (t5 to t6) and, along with this, it decreases the drain current Id of the switching device Q1 (t5 to t6).
Following this, during a resonant operation R2, by the resonant operation of the LC series resonance circuit, the level of the drain voltage Vds of the switching device Q1 shifts from the high level to the low level (t7 to t8). The drain voltage Vds of the switching device Q1 is detected by the input detecting section 1 and the detected signal is outputted to the driving control section 3. Then, at a timing at which the level of the drain current Id or the drain voltage Vds of the switching device Q1 becomes zero, the driving signal S1 is outputted from the driving control section 3 to the driver circuit 121 to change the level of the electric potential at the driving signal input terminal T1 from the low level to the high level (t8).
The change in the level of the electric potential at the driving signal input terminal T1 from the low level to the high level makes the change in the level of the electric potential transmitted to the gates of the p-channel transistor MP42 and the n-channel transistor MN42 through the logic inverting circuit L43 and the buffer L44 to turn-on the p-channel transistor MP42 and, along with this, to turn-off the n-channel transistor MN42. This makes the level of the electric potential at the switching device driving terminal T2 gradually shift from the low level to the high level according to the driving capacity of the p-channel transistor MP42 (t8 to t9).
The gradual shift of the level of the electric potential at the switching device driving terminal T2 from the low level to the high level gradually increases the drain current Id of the switching device Q1 (t8 to t11).
Subsequently, the change in the level of the electric potential at the driving signal input terminal T1 from the high level to the low level (t10) makes the change in the level of the electric potential transmitted to the gates of the p-channel transistor MP42 and the n-channel transistor MN42 through the logic inverting circuit L43 and the buffer L44 to turn-off the p-channel transistor MP42 and, along with this, to turn-on the n-channel transistor MN42. This makes the level of the electric potential at the switching device driving terminal T2 shift from the high level to the low level (t10 to t11).
Then, the shift of the level of the electric potential at the switching device driving terminal T2 from the high level to the low level shifts the level of the drain voltage Vds of the switching device Q1 shown in FIG. 10 from the low level to the high level (t11) and, along with this, decreases the drain current Id of the switching device Q1 (t11).
However, in the related driving system for a switching power supply, as shown in FIG. 11, the lowered driving capacity of the p-channel transistor MP41, although it can reduce the switching noise N2 at the start of the resonant operation R1, increases the switching loss N1 at the resonant operation R2.
While, as shown in FIG. 13, the enhanced driving capacity of the p-channel transistor MP42 reduces the switching loss N1 at the resonant operation R2, it increases the switching noise N2 at the start of the resonant operation.
This causes a problem in the related driving system for a switching power supply in that neither the switching noise N2 at the start of the resonant operation R1 nor the switching loss N1 at the resonant operation can be reduced.
Accordingly, it is an object of the invention to provide a driving system for a switching power supply which can reduce both of the switching noise at the start of the resonant operation and the switching loss N1 at the resonant operation.
Further objects and advantages of the invention will be apparent from the following description of the invention.